|
The Super Nintendo Entertainment System technical specifications〔http://problemkaputt.de/fullsnes.htm〕 describe the various components of the Super Nintendo Entertainment System video game console. The design of the Super NES incorporates graphics and sound co-processors that allow tiling, Mode 7's faux 3D effects, a 32,768 color palette, and 16-bit sound. Individual game cartridges can supply further custom chips as needed. ==Central processing unit== (詳細はCPU is a Nintendo-custom 5A22 processor, based on a 16-bit 65c816 core. The CPU employs a variable bus speed depending on the memory region being accessed for each instruction cycle: the input clock is divided by 6, 8, or 12 to obtain the bus clock rate. Non-access cycles, most register accesses, and some general accesses use the divisor of 6. WRAM accesses and other general accesses use the divisor of 8. Only the controller port serial-access registers use the divisor of 12. The chip has an 8-bit data bus, controlled by two address buses. The 24-bit "Bus A" is used for general accesses, while the 8-bit "Bus B" is used for support chip registers (mainly the video and audio processors).〔 Normally only one bus is used at a time; however, the built-in direct memory access (DMA) unit places a read signal on one bus and a write signal on the other to achieve block transfer speeds of up to 2.68 MB/s.〔This quantity uses the standard decimal meaning of megabyte: 1,000,000 bytes.〕 The DMA unit has 8 independent channels, each of which can be used in two modes. General DMA transfers up to 64 kB〔Unless otherwise specified, kilobyte (kB), megabyte (MB), and megabit (Mbit) are used in the binary sense in this article, referring to quantities of 1,024 or 1,048,576.〕 in one shot, while H-blank DMA (HDMA) transfers 1–4 bytes at the end of each video scanline. HDMA is typically used to change video parameters to achieve effects such as perspective, split-screen, and non-rectangular windowing without tying up the main CPU.〔 The 5A22 also contains the following: an 8-bit parallel I/O port; controller port interface circuits, including both serial and parallel access to controller data; a 16-bit multiplication and division unit; and circuitry for generating non-maskable interrupts on V-blank and IRQ interrupts on calculated screen positions.〔 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Super Nintendo Entertainment System technical specifications」の詳細全文を読む スポンサード リンク
|